Cut Topology-Based FPGA Logic Architecture with Powerful Logic Capacity and Area Efficiency

ACM Transactions on Reconfigurable Technology and Systems. Field-programmable gate arrays (FPGAs) have been an efficient alternative for the implementation of digital circuits. Look-up table (LUT)-based programmable logic blocks (PLBs) serve as the foundation for FPGAs. As increasing the LUT input number to improve performance and logic capacity will introduce exponential area overhead, substantial research has focused on designing more efficient logic architecture. Previous approaches primarily design dedicated hardware by analyzing the frequency distribution of Boolean functions and implementing those with high frequency. However, these approaches face scalability challenges due to the explosive growth in the function space. In this article, we consider the topology of cuts rather than Boolean functions they represent. By identifying topologies that occur commonly in cuts and integrating them with LUTs, we propose a new 8-input PLB architecture, named FLAIC. This architecture incurs only a slight area overhead compared to a 6-LUT while achieving logic capacity comparable to that of an 8-LUT. Post-synthesis results on VTR and Koios benchmarks demonstrate that FLAIC reduces the logic levels by over 20% compared to 6-LUTs. Additionally, post-implementation results show improvement in critical path delay by 11.9% and reduction in the number of Configurable Logic Blocks by 1.5% without sacrificing routability, compared to Intel Stratix 10-like architecture